This invention relates to a semiconductor memory device in which the access time is improved and the power consumption is decreased.
FIG. 1 is a block diagram showing a conventional semiconductor memory device. In FIG. 1, reference numeral 1 designates memory cells which are arranged in matrix form and are shown in detail in FIG. 2; 2a and 2b, pairs of complementary bit lines; 3, word lines which, when selected, render active the memory cells thereon; 4, row decoders for decoding row address data; 6a and 6b, bit line loads connected to the bit lines 2a and 2b, respectively; and 7, power source terminals.
In FIG. 2 showing the memory cell 1, reference characters 8a and 8b designate load elements comprising MOS transistors, resistors, etc; 9a and 9b, inverter transistors; 10a and 10b, access transistors; and 11a and 11b, the storage nodes of the memory cell 1.
The operation of the semiconductor memory device thus organized will now be described with respect to the case where, for instance, the nodes 11a and 11b are at "H" and "L" levels, respectively. First, in the case of reading, the address data of a memory cell to be read is applied to an address signal line 5, so that a desired word line 3 is activated through the row decoder 4, whereupon the access transistor 10b which stores the "L" level is rendered conductive. As a result, current from the power source terminal 7 flows in the bit line load 6b, the bit line 2b, the access transistor 10b and the inverter transistor 9b, thus, accomplishing the reading operation.
In this semiconductor device, all of the memory cells on one and the same line are made active, and therefore currents flow to the memory cells from the power source terminals of all the columns. Accordingly, if a large capacity static RAM having a number of columns is formed, a large amount of current is inevitably consumed.
In order to decrease the current consumption, a semiconductor memory device as shown in FIG. 3 has been proposed in the art. In this device, row decoders 4 are arranged in the middle of a memory cell plane, the word lines are divided into a group of left word lines 3a and a group of right word lines 3b, and only the word lines of a selected one of the right and left memory cell groups are made active, so that current flows in only half of the columns. In FIG. 3, reference characters 12a and 12b designate AND gates for selecting the left word lines 3a and the right word lines 3b, respectively; and 13a and 13b, gate signal lines for opening the AND gates 12a and 12b, respectively.
Devices similar to that shown in FIG. 3 are disclosed in articles by Minato et.al.; Ebel et.al.; and Anami et. al. in the ISSCC Digest of Technical Papers; Feb. 1982; pages 250-251; 254-255; and 256-257; respectively. In each case, the current consumption is cut in half by employing decoders arranged between right and left memory arrays.
FIG. 4 is an explanatory diagram showing the arrangement of a conventional semiconductor memory device formed according to the technical concept of FIG. 3. In this device, the row decoders 4a and 4b are arranged in a plurality of columns, and the word lines 3a through 3d are provided in as many as double the number of columns, so that the number of DC current paths is decreased.
However, the conventional semiconductor device suffers from drawbacks in that, as it requires a number of row decoders, the chip area is necessarily large, and the response characteristic and the yield are insufficient.